The present invention relates generally to the field of memory and in particular to an efficient method of reading data from an SDRAM that is not stored in a DRAM array.
Portable electronic devices have become ubiquitous accoutrements to modern life. Two relentless trends in portable electronic devices are increased functionality and decreased size. Increased functionality demands higher computing power and more memory. The decreasing size of portable electronic devices places a premium on power consumption, as smaller batteries can store and deliver less power. Thus, advances that increase performance and decrease power consumption are advantageous for portable electronic devices.
Most portable electronic devices include Dynamic Random Access Memory (DRAM) to store instructions and data for a processor or other controller. DRAM is the most cost-effective solid-state memory technology available. While the price per bit is lower for mass storage technologies such as disk drives, the high access latency, high power consumption, and high sensitivity to shock or vibration preclude the use of mass storage drives in many portable electronic device applications.
Synchronous DRAM (SDRAM) offers both improved performance and simplified interface design over conventional DRAM by aligning all control signals and data transfer cycles to clock edges. Double data rate (DDR) SDRAM allows data transfers on both rising and falling edges of the clock, providing still higher performance.
Most SDRAM modules include a mode register to store configurable parameters such as CAS latency, burst length, and the like. As SDRAM technology increased in complexity and configurability, many SDRAM modules added an extended mode register to store additional configurable parameters such as Delay Locked Loop (DLL) enable, drive strength, and the like. Both the mode register and extended mode register are write-only. That is, there is no provision for a controller to read the contents of these registers. With the introduction of the mode and extended mode registers, a DRAM module for the first time stored information other than the data written to and read from the DRAM array. Consequently, a new data transfer operation was required.
Many SDRAM modules include Mode Register Set (MRS) and Extended Mode Register Set (EMRS) operations to load the registers with the desired parameters. These operations are commonly implemented by simultaneously driving the CS, RAS, CAS, and WE control signals low, selecting between the MRS and EMRS with bank address bits, and providing the information to be written to the selected register on address lines A0-A11. In most implementations, all DRAM banks must be inactive at the time of the MRS or EMRS command, and no further operation may be directed to the SDRAM module for a specified minimum duration, such as six clock cycles. These restrictions do not adversely impact the SDRAM performance, since due to the nature of the mode and extended mode registers, they are written once upon initialization and never changed.
The third-generation Graphics Double Data Rate industry specification (GDDR3) provides the ability to read information from an SDRAM module other than data stored in the DRAM array. As one option during an EMRS operation, the SDRAM may output a vendor code and version number on the data bus (EMRS write information is transmitted on the address bus). All of the restrictions of the EMRS operation—that all banks be idle and that the operation is followed by a minimum duration, such as six clock cycles, of inactivity—must be observed. Due to the static nature of the information (vendor ID and version number), it only needs to be read once, such as during initialization, and the limitations of the EMRS operation do not significantly affect performance.
A basic aspect of DRAM operation is that the capacitive charge storing data at each bit position must be periodically renewed to preserve the data state. The DRAM array is refreshed by row; some SDRAM modules may refresh the same row in multiple DRAM banks at the same time. Each row in the DRAM array must be refreshed within a specified refresh period. The DRAM rows may be refreshed sequentially once per refresh period, known as a burst refresh. However, this prevents access to the DRAM array for the time necessary to cycle through all of the rows, and imposes a significant performance degradation. Alternatively, refresh cycles directed to each row may be spread evenly throughout the refresh period, interspersed with read and write data transfers. This is known as distributed refresh. Distributed refresh is more commonly implemented, as it imposes less of a performance penalty.
The total required refresh period, and hence the spacing of refresh cycles in a distributed refresh operation, depends on the temperature of the DRAM array dye. As a general rule of thumb, the refresh rate must be doubled for every 10° C. increase in the DRAM array die temperature. The refresh period specified for a SDRAM module is typically that required by the DRAM at its highest anticipated operating temperature. Thus, whenever the DRAM array die is at a lower temperature, the maximum refresh period is longer, and the distributed refresh cycles may be spaced further apart, thus reducing their impact on DRAM read and write accesses. This would both improve processor performance and reduce power consumption by eliminating unnecessary refresh activity.
The synchronous read cycles for accessing data from a SDRAM module that is not stored in a DRAM array may be seamlessly integrated with read and write cycles for accessing “normal” SDRAM data—that is, data stored in a DRAM array on the SDRAM module. By using the synchronous read cycles for accessing data not stored in a DRAM array, the output of a temperature sensor on the SDRAM module may be read with minimal impact on system accesses to data stored in a DRAM array on the SDRAM module. For example, all banks do not need to be closed, and no wait period is imposed on SDRAM accesses following the read cycles, as is the case in accessing extended mode register data via the GDDS3 protocol.
Since the synchronous read cycles for accessing data not stored in a DRAM array are substantially similar, in timing and sequencing, to synchronous read cycles for accessing data that is stored in a DRAM array, the identification and extraction of the returned data not stored in a DRAM array is problematic. SDRAM controllers often function in a pipelined manner, issuing requests for bursts of data, and receiving the data later (i.e., after a delay determined by the CAS latency field of the mode register). Furthermore, many SDRAM controllers further pipeline memory read operations by buffering data from a plurality of read cycles in a FIFO or other buffer, and making the data available to requesting devices after a further delay from when the data is captured from the SDRAM module by the controller.
In most cases, read operations directed to data that is not stored in a DRAM array are not requested by system modules (such as master devices in a bus or crossbar interconnect), and consequently are not forwarded by the SDRAM controller. Rather, data not stored in a DRAM array is often read by a SDRAM controller for its own consumption—that is, to obtain a temperature reading by which to adjust a refresh rate; to obtain the SDRAM module identification to adjust timing parameters; to read the mode or extended mode registers to verify that they were set properly; or the like. Thus, the read data not stored in a DRAM array must be identified and extracted from the stream of read data stored in a DRAM array, which is forwarded to requesting master devices.
One approach to identifying and extracting read data not stored in a DRAM array would be to “trap” the data immediately upon its transfer from the SDRAM memory module to the controller. However, due to the heavily pipelined architecture of many memory controllers, this approach would adversely impact performance, as it would necessitate that the controller halt “normal” SDRAM activity upon issuing a memory access cycle directed to data not stored in a DRAM array, until the data is returned. For maximum performance, the synchronous nature of read cycles directed to data not stored in a DRAM array should be fully exploited by seamlessly intermixing them with normal read accesses. This requires a mechanism for identifying and extracting the data not stored in a DRAM array further down the pipeline, such as when the memory controller extracts read data from a buffer for dispatch to the requesting master device.